Current Work
RISC-V Lightweight Fault Isolation
Leading the RISC-V port of Lightweight Fault Isolation, which enforces memory safety at the OS level through compiler-based validation. Modified LLVM's backend to generate code satisfying security invariants and built runtime sandboxing infrastructure. Presented at RISC-V Summit 2025.
wasm2c Overhead on Embedded Systems
Systematically benchmarking wasm2c compiled code on 32-bit RISC-V embedded systems to characterize bounds-checking overhead. Using QEMU with hardware counters to profile optimizations in GCC and Clang.
Carbon Emissions Analysis of AI Chips
Conducted an in-depth comparison between carbon emissions of digital AI chips and analog-in-memory chips. Analyzed energy consumption, environmental impacts, and efficiency.
Side Projects
Pintos Operating System
Developed core operating system components including threading, synchronization, user programs, virtual memory, and file systems in C. Teaching Assistant for CS 212.
Bare-Metal RISC-V Computer
Built a bare-metal RISC-V system on a Mango Pi from scratch, working with assembly language, memory management, peripheral control, and a custom C-based shell.
Python UI for VMM2 Chip
Collaborated in a team of four to create a Python Flask app and HTML interface for researchers at Sandia National Laboratories. Achieved functional proof of concept for device conductance measurement toward neural network deployment.